This application relies for priority upon Korean Patent Application No. 2000-20982, filed on Apr. 20, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a semiconductor device package. More particularly, the present invention relates to a repairable multi-chip package including a plurality of two-dimensionally mounted chips.
Recently, increases in memory density, i.e., memory storage capacity, have been continually required to keep up with rapid developments in modern digital technology. However, the current rate of increase for memory density does not presently satisfy this pressing demand. In order to improve the memory density, a multi-chip package design including a plurality of bare semiconductor integrated chips has been widely employed in application for DRAMs, SRAMs, Flash memories, and the like.
A multi-chip package for memory cards such as smart media is generally assembled by mounting two or more memory chips within a single package. However, this kind of multi-chip package has the drawback in that it has a low test yield after the assembly process. In other words, compared to a semiconductor package that has only a single memory chip, a multi-chip package has a comparatively low test yield.
One of the reasons for this is that in a multi-chip package, even if there is only one failed chip, or several failed chips among a plurality of chips, the multi-chip package is considered a failure. Because of this, the multi-chip package has a higher failure rate than other packages. Preferably, when the assembled multi-chip package is measured as a failure, only the failed chips should be removed. However, after the assembly process, since the multi-chip package is sealed with the molding resin such as EMC (Epoxy Molding Compound). As a result, in order to remove the failed memory chips, the multi-chip package would have to be disassembled in a way that would destroy them.
In the multi-chip package having at least two chips, there are two methods of increasing the memory capacity. The first method is to broaden the bus width of data, as it is used in the memory module. The second method is retain a given bus width of data, but to broaden the address. As shown in the example below, a multi-chip package 100 in FIG. 1 uses the second method.
FIG. 1 shows a conventional multi-chip package 100, in which two semiconductor chips 10 and 20 are mounted on an upper surface 34 of a substrate 30. As shown in FIG. 1, the multi-chip package 100 is generally employed on a memory card such as a smart media. The chips 10 and 20 are arranged to be coplanar on the upper surface 34 of the substrate 30 and are referred to as xe2x80x9ca first chipxe2x80x9d 10 and xe2x80x9ca second chipxe2x80x9d 20, respectively. The first and second chips 10 and 20 are mounted on the substrate 30 and are molded by a liquid molding resin, thereby forming a molding part 50. The first and second chips 10 and 20 are electrically connected to the substrate 30 by bonding wires 60.
In this design the first and second chips 10 and 20 are memory chips with the same capacitance. A plurality of electrode terminals are formed on both edges of the active surface of each chip 10 and 20. The electrode terminals of the first chip 10 comprise a first power terminal 12, a first ground terminal 13, a second power terminal 14, a most significant bit (MSB) terminal 15, a second ground terminal 16, and a dual terminal 17. The first power terminal 12 and the first ground terminal 13 are arranged on one edge of the active surface of the first chip 10, and the second power terminal 14, the MSB terminal 15, the second ground terminal 16, and the dual terminal 17 are arranged on the opposite edge.
Similarly, the electrode terminals of the second chip 20 comprise a first power terminal 22, a first ground terminal 23, a second power terminal 24, an MSB terminal 25, a second ground terminal 26, and a dual terminal 27. The first power terminal 22 and the first ground terminal 23 are arranged on one edge of the active surface of the second chip 20, and the second power terminal 24, the MSB terminal 25, the second ground terminal 26, and the dual terminal 27 are arranged on the opposite edge.
The first chip 10 and the second chip 20 are designed so that both the first chip 10 and the second chip 20 are dually operated. However, only one chip from among the first and second chips 10 and 20 can be operated at a time.
The substrate 30 comprises a substrate body 32 having an upper surface 34 and a lower surface (not shown), and a plurality of wiring patterns 40. The first chip 10 and the second chip 20 are mounted on the upper surface 34. The wiring patterns 40 are formed on the upper surface 34, and are electrically interconnected to the first chip 10 and the second chip 20. A plurality of external connection terminals (not shown), which are electrically interconnected to the wiring patterns 40 of the upper surface 34, are formed on the lower surface of the substrate 30.
The wiring patterns 40 are dually patterned and simultaneously operate the first chip 10 and the second chip 20. Ground patterns 42 are electrically connected to the first ground terminal 13 of the first chip 10 and to the first ground terminal 23 of the second chip 20, respectively. Power patterns 41 electrically connect the first power terminal 12 of the first chip 10 and the first power terminal 22 of the second chip 20 to each other. In order to prevent interference between the ground patterns 42 and the power patterns 41, a part of the power patterns 41 is formed on the upper surface 34 within the perimeter of the chips 10 and 20. The portion of the power patterns 41 that is formed in this manner is the portion connected from the first power terminal 12 of the first chip 10 to the first power terminal 22 of the second chip 20.
Dual patterns 49 serve to transmit a signal for dual operation of the first and second chips 10 and 20. The dual patterns 48 comprise first dual patterns 47 for connecting the dual terminal 17 and the second ground terminal 16 of the first chip 10 to each other, and second dual patterns 48 for connecting the dual terminal 27 and the second ground terminal 26 of the second chip 20 to each other. In this design, one end of the second dual patterns 48 is connected to the first dual patterns 47.
Most significant bit (MSB) patterns 45 are connected to the MSB terminal 15 for selecting the first chip 10 or the second chip 20. The MSB patterns 45 comprise first MSB patterns 43 for being connected to the second power terminal 14 of the first chip 10 and a second MSB patterns 44 for being connected to the MSB terminal 15 of the first chip and to the second power terminal 24 of the second chip 20. In this design, one end of the second MSB patterns 44 is connected to the first MSB patterns 43 within the perimeter of the molding part 50, and the other end of the second MSB patterns 44 is exposed to the outside before the second power terminal 24 of the second chip 20. Parts of the second MSB patterns 44 between these two ends are formed on the upper surface 34 within the perimeter of the chips 10 and 20.
After mounting the first and second chips 10 and 20 on the upper surface 34 of the substrate body 30 and electrically connecting each chip 10 and 20 to the substrate 30 by the bonding wires 60, the first chip 10 and the second chip 20 are sealed by the molding part 50. As a result, most of the wiring patterns 40 are included within the molding part 50.
During various test processes after the assembly process, the various semiconductor multi-chip packages that are determined to be failures are disposed of. The failures of the packages are classified into two types. One case is a package on which the two chips are both defective (referred to as xe2x80x9cfully-failed packagexe2x80x9d); the other case is a package on which only a single chip is defective (referred to as xe2x80x9cpartially-failed packagexe2x80x9d). However, if a package is proved to be a failure, it is disposed of whether it is a fully-failed package or a partially-failed package.
In the case of partially-failed packages, since most of the wiring patterns are sealed by the molding part, it is difficult to select only a good chip by repairing the wiring patterns. As a result, packages with functional chips are discarded, reducing the yield of the manufacturing process.
Accordingly, an object of the present invention is to repair partially-failed multi-chip packages that have a mix of functional and non-functional chips and to use the repaired multi-chip packages as good packages having good chips.
In order to achieve the foregoing and other objects, the present invention provides a repairable multi-chip package. The repairable multi-chip package comprises a substrate; a first chip formed over the substrate, having a plurality of first terminals; a second chip formed over the substrate, having a plurality of second terminals; a molding part comprising molding resin formed over the first chip and the second chip; and a plurality of wiring patterns formed in the substrate and having portions extending beyond the molding part, the wiring patterns being electrically connected to the first and second chips through the first and second terminals, respectively, wherein the plurality of wiring patterns are arranged such that if one of the first and second chips is non-functional and the other of the first and second chips is functional, the portions of the wiring patterns extending beyond the molding part can be selectively cut to allow the functional chip to operate.
The plurality of first and second terminals each preferably comprise a first power terminal, a first ground terminal, a second power terminal, a most significant bit (MSB) terminal, a second ground terminal, and a dual terminal. The first power terminal and the first ground terminal of the first chip are preferably formed on a first edge of a first active surface of the first chip; the second power terminal, the MSB terminal, the second ground terminal, and the dual terminal of the first chip are preferably formed on a second edge of the first active surface; the first power terminal and the first ground terminal of the second are preferably formed on a first edge of a second active surface of the second chip; and the second power terminal, the MSB terminal, the second ground terminal, and the dual terminal of the first chip are preferably formed on a second edge of the second active surface.
The wiring patterns may further comprise a plurality of ground patterns for connecting the first and second chips to a ground voltage; a plurality of power patterns for connecting the first and second chip to a supply voltage; a plurality of dual patterns for transmitting a signal for the dual operation of the first and second chips to the first and second chips; and a plurality of most significant bit (MSB) patterns for selecting one of the first and second chips.
The plurality of ground patterns may comprise a first ground pattern connected to the first ground terminal of the first chip; and a second ground pattern connected to the second ground terminal of the second chip.
The plurality of power patterns may comprise a first power pattern connected to the first power terminal of the first chip and extending beyond the molding part; and a second power pattern connected to the first power terminal of the second chip, and to the first power pattern beyond the molding part.
The second power pattern is preferably formed inside of the plurality of ground patterns to prevent interference between the second power pattern and the first ground pattern.
The plurality of dual patterns may comprise a first dual pattern connected to the dual terminal and the second ground terminal of the first chip and extending beyond the molding part; a second dual pattern connected to the dual terminal and the second ground terminal of the second chip and extending beyond the molding part; and a third dual pattern connecting the first and second dual patterns together. The plurality of dual patterns may further comprise a fourth dual pattern connected to the second ground terminal of the first chip; and a fifth dual pattern connected to the second ground terminal of the second chip. In this case, the third dual pattern connects the first, second, fourth, and fifth dual patterns together.
The plurality of MSB patterns may comprise a plurality of first MSB patterns connected to the MSB terminal and the second ground terminal of the first chip and extending beyond the molding part; a second MSB pattern formed beyond the molding part and connected to the first MSB patterns; and a third MSB pattern connected to the second power terminal of the second chip, and to the second MSB pattern between two of the first MSB patterns. A portion of the third MSB pattern is preferably formed within the perimeter of the first and second chips.
The wiring patterns are preferably formed such that if the first chip is a functioning chip and the second chip is a non-functioning chip, the second chip can be isolated by cutting the second power pattern, the third MSB pattern, the first dual pattern, and the second dual pattern, all beyond the molding part.
The wiring patterns are also preferably formed such that if the first chip is a nonfunctioning chip and the second chip is a functioning chip, the first chip can be isolated by cutting the first power pattern, the first MSB patterns, the first dual pattern, and the second dual pattern, all beyond the molding part.